/* * DIO96 */ #ifndef _DIO96_H_ #define _DIO96_H_ // According to dio96 reference documentation #define DIO96_VENDOR 0x1093 #define DIO96_ID 0x0160 #define DIO96_CONF 0x92 #define BASE_ADDR baseptr1 #define PORTA_ADDR BASE_ADDR + 0x00 // Port A, aka. Port 0 #define PORTB_ADDR BASE_ADDR + 0x01 // Port B, aka. Port 1 #define PORTC_ADDR BASE_ADDR + 0x02 // Port C, aka. Port 2 #define CNFG_ADDR BASE_ADDR + 0x03 // Config Register /* PPI B */ #define B_PORTA_ADDR BASE_ADDR + 0x04 // PPI B Port A, aka. Port 3 #define B_PORTB_ADDR BASE_ADDR + 0x05 // PPI B Port B, aka. Port 4 #define B_PORTC_ADDR BASE_ADDR + 0x06 // PPI B Port C, aka. Port 5 #define B_CNFG_ADDR BASE_ADDR + 0x07 // PPI B Config Port /* PPI C */ #define C_PORTA_ADDR BASE_ADDR + 0x08 // PPI C Port A, aka. Port 6 #define C_PORTB_ADDR BASE_ADDR + 0x09 // PPI C Port B, aka. Port 7 #define C_PORTC_ADDR BASE_ADDR + 0x0A // PPI C Port C, aka. Port 8 #define C_CNFG_ADDR BASE_ADDR + 0x0B // PPI C Config Port /* PPI D */ #define D_PORTB_ADDR BASE_ADDR + 0x0D // PPI D Port B, aka. Port 10 #define D_PORTC_ADDR BASE_ADDR + 0x0E // PPI D Port C, aka. Port 11 #define D_CNFG_ADDR BASE_ADDR + 0x0F // PPI D Config Port /* Counter/Timer */ #define CLOCKA BASE_ADDR + 0x10 // Clock or Counter 0 #define CLOCKB BASE_ADDR + 0x11 // Clock or Counter 1 #define CLOCKC BASE_ADDR + 0x12 // Clock or Counter 2 #define CLOCK_CTRL BASE_ADDR + 0x13 // Clock or Counter Control /* Interrupt control */ #define INTR_CTRL1 BASE_ADDR + 0x14 // First interrupt control reg #define INTR_CTRL2 BASE_ADDR + 0x15 // Second interrupt control reg #endif